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| author |   Andre Guedes <andre.guedes@intel.com> | 2020-03-06 15:54:03 -0800 |
|---|---|---|
| committer |   Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2020-04-17 10:19:24 -0700 |
| commit | 27945ebe5b980f796fa04dd61511796ac5b80cc2 (patch) | |
| tree | 0cfd54787d5e318d220d6992bcced49d86392dee /drivers/net/ethernet/intel/igc/igc_defines.h | |
| parent | igc: Remove copper fiber switch control (diff) | |
| download | linux-dev-27945ebe5b980f796fa04dd61511796ac5b80cc2.tar.xz linux-dev-27945ebe5b980f796fa04dd61511796ac5b80cc2.zip | |
igc: Fix NFC queue redirection support
The support for ethtool Network Flow Classification (NFC) queue
redirection based on destination MAC address is currently broken in IGC.
For instance, if we add the following rule, matching frames aren't
enqueued on the expected rx queue.
$ ethtool -N IFNAME flow-type ether dst 3c:fd:fe:9e:7f:71 queue 2
The issue here is due to the fact that igc_rar_set_index() is missing
code to enable the queue selection feature from Receive Address High
(RAH) register. This patch adds the missing code and fixes the issue.
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Acked-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igc/igc_defines.h')
| -rw-r--r-- | drivers/net/ethernet/intel/igc/igc_defines.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 42fe4d75cc0d..af0c03d77a39 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -63,8 +63,11 @@ * (RAR[15]) for our directed address used by controllers with * manageability enabled, allowing us room for 15 multicast addresses. */ +#define IGC_RAH_QSEL_MASK 0x000C0000 +#define IGC_RAH_QSEL_SHIFT 18 +#define IGC_RAH_QSEL_ENABLE BIT(28) #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ -#define IGC_RAH_POOL_1 0x00040000 + #define IGC_RAL_MAC_ADDR_LEN 4 #define IGC_RAH_MAC_ADDR_LEN 2 |