diff options
| author |   Alexander Duyck <alexander.h.duyck@intel.com> | 2011-07-15 07:29:44 +0000 |
|---|---|---|
| committer |   Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-09-15 21:26:16 -0700 |
| commit | 8132b54e46259cfc6579ba11c5e3efffda64110b (patch) | |
| tree | 10126b998408f47db9b4ea8815536fa6a28bc9ef /drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | |
| parent | ixgbe: Update TXDCTL configuration to correctly handle WTHRESH (diff) | |
| download | linux-dev-8132b54e46259cfc6579ba11c5e3efffda64110b.tar.xz linux-dev-8132b54e46259cfc6579ba11c5e3efffda64110b.zip | |
ixgbe: cleanup reset paths
The reset paths are overly complicated and are either missing steps or
contain extra unnecessary steps such as reading MAC address twice. This
change is meant to help clean up the reset paths an get things functioning
correctly.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c')
| -rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 0d4e38264492..22504f2db25e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -820,8 +820,8 @@ mac_reset_top: * Issue global reset to the MAC. This needs to be a SW reset. * If link reset is used, it might reset the MAC when mng is using it */ - ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); - IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); + ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; + IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_FLUSH(hw); /* Poll for reset bit to self-clear indicating reset is complete */ @@ -836,21 +836,18 @@ mac_reset_top: hw_dbg(hw, "Reset polling failed to complete.\n"); } + msleep(50); + /* * Double resets are required for recovery from certain error * conditions. Between resets, it is necessary to stall to allow time - * for any pending HW events to complete. We use 1usec since that is - * what is needed for ixgbe_disable_pcie_master(). The second reset - * then clears out any effects of those events. + * for any pending HW events to complete. */ if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; - udelay(1); goto mac_reset_top; } - msleep(50); - gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); |