diff options
| author |   Harman Kalra <hkalra@marvell.com> | 2021-08-26 18:03:40 +0530 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2021-08-27 12:41:13 +0100 |
| commit | 49d6baea798672ae42f73e4662ad792797339ad6 (patch) | |
| tree | e46072ec1ba6d7b68ec872303610a31fd2336a1b /drivers/net/ethernet/marvell/octeontx2/af/rvu.h | |
| parent | phy: marvell: phy-mvebu-a3700-comphy: Remove unsupported modes (diff) | |
| download | linux-dev-49d6baea798672ae42f73e4662ad792797339ad6.tar.xz linux-dev-49d6baea798672ae42f73e4662ad792797339ad6.zip | |
octeontx2-af: cn10K: support for sched lmtst and other features
Enhancing the mailbox scope to support important configurations
like enabling scheduled LMTST, disable LMTLINE prefetch, disable
early completion for ordered LMTST, as per request from the
application. On FLR these configurations will be reset to default.
This patch also adds the 95XXO silicon version to octeontx2 silicon
list.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index a85d7eb1ef77..31c20c917a0b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -245,6 +245,7 @@ struct rvu_pfvf { u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ u8 lbkid; /* NIX0/1 lbk link ID */ u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ + u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ unsigned long flags; struct sdp_node_info *sdp_info; }; @@ -556,9 +557,10 @@ static inline bool is_rvu_95xx_A0(struct rvu *rvu) */ #define PCI_REVISION_ID_96XX 0x00 #define PCI_REVISION_ID_95XX 0x10 -#define PCI_REVISION_ID_LOKI 0x20 +#define PCI_REVISION_ID_95XXN 0x20 #define PCI_REVISION_ID_98XX 0x30 #define PCI_REVISION_ID_95XXMM 0x40 +#define PCI_REVISION_ID_95XXO 0xE0 static inline bool is_rvu_otx2(struct rvu *rvu) { @@ -567,8 +569,8 @@ static inline bool is_rvu_otx2(struct rvu *rvu) u8 midr = pdev->revision & 0xF0; return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || - midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || - midr == PCI_REVISION_ID_95XXMM); + midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || + midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); } static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, |