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author | Hariprasad Kelam <hkelam@marvell.com> | 2021-08-17 10:14:52 +0530 |
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committer | David S. Miller <davem@davemloft.net> | 2021-08-17 10:06:33 +0100 |
commit | 99b8e5479d499bb572538f0f290e720315b78f61 (patch) | |
tree | 4c5463c8a81897dd80591e5c2260fd86a1a544ac /drivers/net/ethernet/marvell/octeontx2/af/rvu.h | |
parent | octeontx2-af: Allocate low priority entries for PF (diff) | |
download | linux-dev-99b8e5479d499bb572538f0f290e720315b78f61.tar.xz linux-dev-99b8e5479d499bb572538f0f290e720315b78f61.zip |
octeontx2-af: cn10K: Get NPC counters value
The way SW can identify the number NPC counters supported by silicon
has changed for CN10K. This patch addresses this reading appropriate
registers to find out number of counters available.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu.h')
-rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index 95591e77aea8..d88f595e63b0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -356,6 +356,7 @@ struct rvu_hwinfo { u16 npc_counters; /* No of match stats counters */ u32 lbk_bufsize; /* FIFO size supported by LBK */ bool npc_ext_set; /* Extended register set */ + u64 npc_stat_ena; /* Match stats enable bit */ struct hw_cap cap; struct rvu_block block[BLK_COUNT]; /* Block info */ |