diff options
| author |   Geetha sowjanya <gakula@marvell.com> | 2021-02-11 21:28:26 +0530 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2021-02-11 14:55:03 -0800 |
| commit | 6e8ad4387da5760f0737ec21452624f653272ed9 (patch) | |
| tree | ab465d00d7acc0bd661867cd071f84fd8c905c87 /drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | |
| parent | octeontx2-pf: cn10k: Initialise NIX context (diff) | |
| download | linux-dev-6e8ad4387da5760f0737ec21452624f653272ed9.tar.xz linux-dev-6e8ad4387da5760f0737ec21452624f653272ed9.zip | |
octeontx2-pf: cn10k: Map LMTST region
On CN10K platform transmit/receive buffer alloc and free from/to hardware
had changed to support burst operation. Whereas pervious silicon's only
support single buffer free at a time.
To Support the same firmware allocates a DRAM region for each PF/VF for
storing LMTLINES. These LMTLINES are used for NPA batch free and for
flushing SQE to the hardware.
PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed
by its VFs mbox memory. The size of region varies from 2KB to 256KB based
on number of LMTLINES configured.
This patch adds support for
- Mapping PF/VF LMTST region.
- Reserves 0-71 (RX + TX + XDP) LMTST lines for NPA batch
free operation.
- Reserves 72-512 LMTST lines for NIX SQE flush.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 3542f2d6c698..9ac9b420dd95 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -209,7 +209,14 @@ struct otx2_hw { u8 lbk_links; /* No. of LBK links present in HW */ #define HW_TSO BIT_ULL(0) #define CN10K_MBOX BIT_ULL(1) +#define CN10K_LMTST BIT_ULL(2) unsigned long cap_flag; + +#define LMT_LINE_SIZE 128 +#define NIX_LMTID_BASE 72 /* RX + TX + XDP */ + void __iomem *lmt_base; + u64 *npa_lmt_base; + u64 *nix_lmt_base; }; struct otx2_vf_config { @@ -319,6 +326,10 @@ struct otx2_nic { /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ int nix_blkaddr; + /* LMTST Lines info */ + u16 tot_lmt_lines; + u16 nix_lmt_lines; + u32 nix_lmt_size; struct otx2_ptp *ptp; struct hwtstamp_config tstamp; @@ -384,8 +395,10 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) pfvf->hw.rq_skid = 600; pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); } - if (!is_dev_otx2(pfvf->pdev)) + if (!is_dev_otx2(pfvf->pdev)) { __set_bit(CN10K_MBOX, &hw->cap_flag); + __set_bit(CN10K_LMTST, &hw->cap_flag); + } } /* Register read/write APIs */ |