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| author |   Geetha sowjanya <gakula@marvell.com> | 2021-09-28 11:25:26 +0530 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2021-09-28 14:10:24 +0100 |
| commit | af3826db74d184bc9c2c9d3ff34548e5f317a6f3 (patch) | |
| tree | 836de45caa99a753010ba58e732f6d1969f731e5 /drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | |
| parent | Merge branch 'octeontx2-af-external-ptp-clock' (diff) | |
| download | linux-dev-af3826db74d184bc9c2c9d3ff34548e5f317a6f3.tar.xz linux-dev-af3826db74d184bc9c2c9d3ff34548e5f317a6f3.zip | |
octeontx2-pf: Use hardware register for CQE count
Current driver uses software CQ head pointer to poll on CQE
header in memory to determine if CQE is valid. Software needs
to make sure, that the reads of the CQE do not get re-ordered
so much that it ends up with an inconsistent view of the CQE.
To ensure that DMB barrier after read to first CQE cacheline
and before reading of the rest of the CQE is needed.
But having barrier for every CQE read will impact the performance,
instead use hardware CQ head and tail pointers to find the
valid number of CQEs.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 0a792fce55f1..069d1b925102 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -343,6 +343,7 @@ struct otx2_nic { #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) u64 flags; + u64 *cq_op_addr; struct otx2_qset qset; struct otx2_hw hw; |