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authorEli Britstein <elibr@mellanox.com>2018-11-18 14:21:46 +0200
committerSaeed Mahameed <saeedm@mellanox.com>2018-12-11 14:52:20 -0800
commit8c4dc42bf6e4ffeda49cf5e26bfc991b548fc0aa (patch)
treee90164d7dc5d82b5b4377d06984889951898dfc3 /drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
parentnet/mlx5e: Allow association of a flow to multiple encaps (diff)
downloadlinux-dev-8c4dc42bf6e4ffeda49cf5e26bfc991b548fc0aa.tar.xz
linux-dev-8c4dc42bf6e4ffeda49cf5e26bfc991b548fc0aa.zip
net/mlx5e: Support multiple encapsulations for a TC flow
Currently a flow is associated with a single encap structure. The FW extended destination features enables the driver to associate a flow with multiple encap instances. Change the encap id field from a flow scope to a per destination value in the flow attributes struct. Use the encaps array to associate a flow table entry with multiple encap entries. Update the neigh logic to offload only if all encapsulations used in a flow are connected, and un-offload upon the first one disconnected. Note that the driver can now support up to two encap destinations. Signed-off-by: Eli Britstein <elibr@mellanox.com> Reviewed-by: Oz Shlomo <ozsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/eswitch.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/eswitch.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
index 39363d4662b3..87c9dea9bccf 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
@@ -283,6 +283,7 @@ enum mlx5_flow_match_level {
enum {
MLX5_ESW_DEST_ENCAP = BIT(0),
+ MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
};
struct mlx5_esw_flow_attr {
@@ -298,11 +299,11 @@ struct mlx5_esw_flow_attr {
u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
u8 total_vlan;
bool vlan_handled;
- u32 encap_id;
struct {
u32 flags;
struct mlx5_eswitch_rep *rep;
struct mlx5_core_dev *mdev;
+ u32 encap_id;
} dests[MLX5_MAX_FLOW_FWD_VPORTS];
u32 mod_hdr_id;
u8 match_level;