diff options
| author |   Danielle Ratson <danieller@nvidia.com> | 2021-02-25 18:57:20 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2021-02-26 15:47:53 -0800 |
| commit | ae9b24ddb69b4e31cda1b5e267a5a08a1db11717 (patch) | |
| tree | 3053bb3b02fad5959dd5cebc4c8ab167041921a0 /drivers/net/ethernet/mellanox/mlxsw/switchx2.c | |
| parent | selftests: forwarding: Fix race condition in mirror installation (diff) | |
| download | linux-dev-ae9b24ddb69b4e31cda1b5e267a5a08a1db11717.tar.xz linux-dev-ae9b24ddb69b4e31cda1b5e267a5a08a1db11717.zip | |
mlxsw: spectrum_ethtool: Add an external speed to PTYS register
Currently, only external bits are added to the PTYS register, whereas
there is one external bit that is wrongly marked as internal, and so was
recently removed from the register.
Add that bit to the PTYS register again, as this bit is no longer
internal.
Its removal resulted in '100000baseLR4_ER4/Full' link mode no longer
being supported, causing a regression on some setups.
Fixes: 5bf01b571cf4 ("mlxsw: spectrum_ethtool: Remove internal speeds from PTYS register")
Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reported-by: Eddie Shklaer <eddies@nvidia.com>
Tested-by: Eddie Shklaer <eddies@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/switchx2.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/switchx2.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/switchx2.c b/drivers/net/ethernet/mellanox/mlxsw/switchx2.c index 40e2e79d4517..131b2a53d261 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/switchx2.c +++ b/drivers/net/ethernet/mellanox/mlxsw/switchx2.c @@ -613,7 +613,8 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { { .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 | MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | - MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, + MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | + MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, .speed = 100000, }, }; |