diff options
| author |   Claudiu Manoil <claudiu.manoil@nxp.com> | 2019-11-14 17:03:21 +0200 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2019-11-15 12:32:16 -0800 |
| commit | dc3de2a294eab8b1375f96eb4cf2a1d5edfcc9ab (patch) | |
| tree | 7ba8008564e6b6dfafe0d21608aae23aec6f5212 /drivers/net/ethernet/mscc/ocelot.c | |
| parent | net: mscc: ocelot: move resource ioremap and regmap init to common code (diff) | |
| download | linux-dev-dc3de2a294eab8b1375f96eb4cf2a1d5edfcc9ab.tar.xz linux-dev-dc3de2a294eab8b1375f96eb4cf2a1d5edfcc9ab.zip | |
net: mscc: ocelot: filter out ocelot SoC specific PCS config from common path
The adjust_link routine should be generic enough to be (re)used by
any SoC that integrates a switch core compatible with the Ocelot
core switch driver. Currently all configurations are generic except
for the PCS settings that are SoC specific. Move these out to the
Ocelot SoC/board instance.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mscc/ocelot.c')
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 3e7a2796c37d..2b6792ab0eda 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -455,23 +455,8 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port, ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), DEV_MAC_HDX_CFG); - /* Disable HDX fast control */ - ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, - DEV_PORT_MISC); - - /* SGMII only for now */ - ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, - PCS1G_MODE_CFG); - ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); - - /* Enable PCS */ - ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); - - /* No aneg on SGMII */ - ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); - - /* No loopback */ - ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); + if (ocelot->ops->pcs_init) + ocelot->ops->pcs_init(ocelot, port); /* Set Max Length and maximum tags allowed */ ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN, |