diff options
| author |   Carl Heymann <carl.heymann@netronome.com> | 2017-12-04 23:34:21 +0100 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2017-12-05 15:01:03 -0500 |
| commit | 60b84a9b3889a55503c6ffac56d69ecc060ad3b5 (patch) | |
| tree | 147cfb71ebf595a78163a827827302ff5103d919 /drivers/net/ethernet/netronome/nfp/nfp_asm.h | |
| parent | nfp: dump CPP, XPB and direct ME CSRs (diff) | |
| download | linux-dev-60b84a9b3889a55503c6ffac56d69ecc060ad3b5.tar.xz linux-dev-60b84a9b3889a55503c6ffac56d69ecc060ad3b5.zip | |
nfp: dump indirect ME CSRs
- The spec defines CSR address ranges for indirect ME CSRs. For Each TLV
chunk in the spec, dump a chunk that includes the spec and the data
over the defined address range.
- Each indirect CSR has 8 contexts. To read one context, first write the
context to a specific derived address, read it back, and then read the
register value.
- For each address, read and dump all 8 contexts in this manner.
Signed-off-by: Carl Heymann <carl.heymann@netronome.com>
Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Simon Horman <simon.horman@netronome.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/netronome/nfp/nfp_asm.h')
| -rw-r--r-- | drivers/net/ethernet/netronome/nfp/nfp_asm.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/netronome/nfp/nfp_asm.h b/drivers/net/ethernet/netronome/nfp/nfp_asm.h index 98803f9f40b6..3387e6926eb0 100644 --- a/drivers/net/ethernet/netronome/nfp/nfp_asm.h +++ b/drivers/net/ethernet/netronome/nfp/nfp_asm.h @@ -262,6 +262,7 @@ enum lcsr_wr_src { #define OP_CARB_BASE 0x0e000000000ULL #define OP_CARB_OR 0x00000010000ULL +#define NFP_CSR_CTX_PTR 0x20 #define NFP_CSR_ACT_LM_ADDR0 0x64 #define NFP_CSR_ACT_LM_ADDR1 0x6c #define NFP_CSR_ACT_LM_ADDR2 0x94 @@ -382,4 +383,13 @@ int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg, int nfp_ustore_check_valid_no_ecc(u64 insn); u64 nfp_ustore_calc_ecc_insn(u64 insn); +#define NFP_IND_ME_REFL_WR_SIG_INIT 3 +#define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0) +#define NFP_IND_NUM_CONTEXTS 8 + +static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset) +{ + return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR; +} + #endif |