diff options
| author |   Ben Hutchings <bhutchings@solarflare.com> | 2012-09-19 17:47:08 +0100 |
|---|---|---|
| committer | Ben Hutchings <bhutchings@solarflare.com> | 2013-08-29 18:12:16 +0100 |
| commit | 9c51716512c1e73523b685f389fbb748c15436e4 (patch) | |
| tree | 154b84e2e6a024e43f6673553d3528e0b5314c31 /drivers/net/ethernet/sfc/io.h | |
| parent | sfc: Extend struct efx_tx_buffer to allow pushing option descriptors (diff) | |
| download | linux-dev-9c51716512c1e73523b685f389fbb748c15436e4.tar.xz linux-dev-9c51716512c1e73523b685f389fbb748c15436e4.zip | |
sfc: Add EF10 register and structure definitions
Also update comments and assertions in io.h:
- EF10 does not have a general BIU collector and does not have the
bug affecting TIMER_COMMAND_REG[0] on Falcon/Siena
- The WPTR field moved within RX_DESC_UPD_REG and TX_DESC_UPD_REG.
Adjust efx_writed_page() accordingly
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/ethernet/sfc/io.h')
| -rw-r--r-- | drivers/net/ethernet/sfc/io.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/net/ethernet/sfc/io.h b/drivers/net/ethernet/sfc/io.h index 19e8b95b7af6..416ee4a469c4 100644 --- a/drivers/net/ethernet/sfc/io.h +++ b/drivers/net/ethernet/sfc/io.h @@ -20,7 +20,7 @@ * ************************************************************************** * - * Notes on locking strategy: + * Notes on locking strategy for the Falcon architecture: * * Many CSRs are very wide and cannot be read or written atomically. * Writes from the host are buffered by the Bus Interface Unit (BIU) @@ -54,6 +54,12 @@ * register while the collector already holds values for some other * register, the write is discarded and the collector maintains its * current state. + * + * The EF10 architecture exposes very few registers to the host and + * most of them are only 32 bits wide. The only exceptions are the MC + * doorbell register pair, which has its own latching, and + * TX_DESC_UPD, which works in a similar way to the Falcon + * architecture. */ #if BITS_PER_LONG == 64 @@ -237,8 +243,8 @@ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ page) -/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of - * RX_DESC_UPD or TX_DESC_UPD) +/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the + * high bits of RX_DESC_UPD or TX_DESC_UPD) */ static inline void _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, @@ -249,8 +255,12 @@ _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, #define efx_writed_page(efx, value, reg, page) \ _efx_writed_page(efx, value, \ reg + \ - BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \ - && (reg) != 0xa1c), \ + BUILD_BUG_ON_ZERO((reg) != 0x400 && \ + (reg) != 0x420 && \ + (reg) != 0x830 && \ + (reg) != 0x83c && \ + (reg) != 0xa18 && \ + (reg) != 0xa1c), \ page) /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug |