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authorWong, Vee Khee <vee.khee.wong@intel.com>2021-03-26 01:39:16 +0800
committerDavid S. Miller <davem@davemloft.net>2021-03-25 17:37:30 -0700
commit6ccf12ae111e49324b439410066e8cc359aeee6d (patch)
tree1c268024e10fcf3e50158107d46348d624c3ed23 /drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
parentstmmac: intel: add support for multi-vector msi and msi-x (diff)
downloadlinux-dev-6ccf12ae111e49324b439410066e8cc359aeee6d.tar.xz
linux-dev-6ccf12ae111e49324b439410066e8cc359aeee6d.zip
net: stmmac: use interrupt mode INTM=1 for multi-MSI
For interrupt mode INTM=0, TX/RX transfer complete will trigger signal not only on sbd_perch_[tx|rx]_intr_o (Transmit/Receive Per Channel) but also on the sbd_intr_o (Common). As for multi-MSI implementation, setting interrupt mode INTM=1 is more efficient as each TX intr and RX intr (TI/RI) will be handled by TX/RX ISR without the need of calling the common MAC ISR. Updated the TX/RX NORMAL interrupts status checking process as the NIS status bit is not asserted for any RI/TI events for INTM=1. Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com> Co-developed-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index 5c0c53832adb..05481eb13ba6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -25,6 +25,9 @@
#define DMA_TBS_CTRL 0x00001050
/* DMA Bus Mode bitmap */
+#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
+#define DMA_BUS_MODE_INTM_SHIFT 16
+#define DMA_BUS_MODE_INTM_MODE1 0x1
#define DMA_BUS_MODE_SFT_RESET BIT(0)
/* DMA SYS Bus Mode bitmap */