diff options
| author |   Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2012-11-25 23:10:43 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2012-11-26 17:22:12 -0500 |
| commit | 62a2ab935c8d0f8643d02d3696abc401b5da6206 (patch) | |
| tree | 621848d4f395f224faa16e576d5f5b93a63f01a2 /drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h | |
| parent | stmmac: add the initial tx coalesce schema (diff) | |
| download | linux-dev-62a2ab935c8d0f8643d02d3696abc401b5da6206.tar.xz linux-dev-62a2ab935c8d0f8643d02d3696abc401b5da6206.zip | |
stmmac: add Rx watchdog support to mitigate the DMA irqs
GMAC devices newer than databook 3.40 has an embedded timer
that can be used for mitigating the number of interrupts.
So this patch adds this optimizations.
At any rate, the Rx watchdog can be disable (on bugged HW) by
passing from the platform the riwt_off field.
In this implementation the rx timer stored in the Reg9 is fixed
to the max value. This will be tuned by using ethtool.
V2: added a platform parameter to force to disable the rx-watchdog
for example on new core where it is bugged.
V3: do not disable NAPI when Rx watchdog is used.
V4: a new extra statistic field has been added to show the early
receive status in the interrupt handler.
This patch also adds an extra check to avoid to call
napi_schedule when the DMA_INTR_ENA_RIE bit is disabled in the
Interrupt Mask register.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h index e49c9a0fd6ff..807f30371e49 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h @@ -35,7 +35,10 @@ #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */ #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */ #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */ -#define DMA_AXI_BUS_MODE 0x00001028 /* AXI Bus Mode */ +/* Rx watchdog register */ +#define DMA_RX_WATCHDOG 0x00001024 +/* AXI Bus Mode */ +#define DMA_AXI_BUS_MODE 0x00001028 #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */ #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */ #define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */ |