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authorIvan Khoronzhuk <ivan.khoronzhuk@linaro.org>2016-06-17 13:25:39 +0300
committerDavid S. Miller <davem@davemloft.net>2016-06-17 21:27:57 -0700
commit1793331e0943f1ddd8649dd1ccea11f3f267d371 (patch)
tree88647e5114ccf28c90709879635e332d22e571fe /drivers/net/ethernet/ti/cpsw.h
parenttipc: potential shift wrapping bug in map_set() (diff)
downloadlinux-dev-1793331e0943f1ddd8649dd1ccea11f3f267d371.tar.xz
linux-dev-1793331e0943f1ddd8649dd1ccea11f3f267d371.zip
net: ethernet: ti: cpsw: remove rx_descs property
There is no reason in rx_descs property because davinici_cpdma driver splits pool of descriptors equally between tx and rx channels. That is, if number of descriptors 256, 128 of them are for rx channels. While receiving, the descriptor is freed to the pool and then allocated with new skb. And if in DT the "rx_descs" is set to 64, then 128 - 64 = 64 descriptors are always in the pool and cannot be used, for tx, for instance. It's not correct resource usage, better to set it to half of pool, then the rx pool can be used in full. It will not have any impact on performance, as anyway, the "redundant" descriptors were unused. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/ti/cpsw.h')
-rw-r--r--drivers/net/ethernet/ti/cpsw.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
index e50afd1b2eda..16b54c6f32c2 100644
--- a/drivers/net/ethernet/ti/cpsw.h
+++ b/drivers/net/ethernet/ti/cpsw.h
@@ -35,7 +35,6 @@ struct cpsw_platform_data {
u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */
u32 ale_entries; /* ale table size */
u32 bd_ram_size; /*buffer descriptor ram size */
- u32 rx_descs; /* Number of Rx Descriptios */
u32 mac_control; /* Mac control register */
u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
bool dual_emac; /* Enable Dual EMAC mode */