diff options
author | 2009-09-19 11:27:32 +0200 | |
---|---|---|
committer | 2009-09-19 11:28:41 +0200 | |
commit | 929bf0d0156562ce631728b6fa53d68004d456d2 (patch) | |
tree | 739063990a8077b29ef97e69d73bce94573daae4 /drivers/net/igb/e1000_defines.h | |
parent | sched_clock: Make it NMI safe (diff) | |
parent | pty_write: don't do a tty_wakeup() when the buffers are full (diff) | |
download | linux-dev-929bf0d0156562ce631728b6fa53d68004d456d2.tar.xz linux-dev-929bf0d0156562ce631728b6fa53d68004d456d2.zip |
Merge branch 'linus' into perfcounters/core
Merge reason: Bring in tracing changes we depend on.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 3bda3db73f1f..cb916833f303 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h @@ -44,7 +44,7 @@ #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ /* Extended Device Control */ -#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ /* Physical Func Reset Done Indication */ #define E1000_CTRL_EXT_PFRSTD 0x00004000 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 @@ -435,6 +435,12 @@ /* Flow Control */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ +/* PCI Express Control */ +#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 +#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 +#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 +#define E1000_GCR_CAP_VER2 0x00040000 + /* PHY Control Register */ #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ @@ -569,9 +575,11 @@ /* PCI/PCI-X/PCI-EX Config space */ #define PCIE_LINK_STATUS 0x12 +#define PCIE_DEVICE_CONTROL2 0x28 #define PCIE_LINK_WIDTH_MASK 0x3F0 #define PCIE_LINK_WIDTH_SHIFT 4 +#define PCIE_DEVICE_CONTROL2_16ms 0x0005 #define PHY_REVISION_MASK 0xFFFFFFF0 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |