diff options
| author |   Stephen Hemminger <shemminger@vyatta.com> | 2009-10-29 06:37:07 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2009-10-29 22:57:27 -0700 |
| commit | d6b54d241c558483302616ac1d997806795513e4 (patch) | |
| tree | ca94169c75aa3f3459d1f6e7316fb60d4bdce01b /drivers/net/sky2.h | |
| parent | sky2: add register definitions for new chips (diff) | |
| download | linux-dev-d6b54d241c558483302616ac1d997806795513e4.tar.xz linux-dev-d6b54d241c558483302616ac1d997806795513e4.zip | |
sky2: fix receive pause thresholds
Program the receive pause thresholds differently depending on
chip version. This cloned from from the vendor (GPL) driver.
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sky2.h')
| -rw-r--r-- | drivers/net/sky2.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index e13da94d19a3..365d79c7d834 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -808,10 +808,11 @@ enum { RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ - RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ + RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */ + RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */ RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ - RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ - RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ + RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ + RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ |