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| author |   Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2010-09-17 03:23:40 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2010-09-17 16:12:57 -0700 |
| commit | ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06a (patch) | |
| tree | 9ee381c887f2bc585c103a34b349d85fd95a2567 /drivers/net/stmmac/dwmac1000_core.c | |
| parent | stmmac: add CSR Clock range selection (diff) | |
| download | linux-dev-ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06a.tar.xz linux-dev-ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06a.zip | |
stmmac: consolidate and tidy-up the COE support
The first version of the driver had hard-coded the logic
for handling the checksum offloading.
This was designed according to the chips included in
the STM platforms where:
o MAC10/100 supports no COE at all.
o GMAC fully supports RX/TX COE.
This is not good for other chip configurations where,
for example, the mac10/100 supports the tx csum in HW
or when the GMAC has no IPC.
Thanks to Johannes Stezenbach; he provided me a first
draft of this patch that only reviewed the IPC for the
GMAC devices.
This patch also helps on SPEAr platforms where the
MAC10/100 can perform the TX csum in HW.
Thanks to Deepak SIKRI for his support on this.
In the end, GMAC devices for STM platforms have
a bugged Jumbo frame support that needs to have
the Tx COE disabled for oversized frames (due to
limited buffer sizes). This information is also
passed through the driver's platform structure.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Johannes Stezenbach <js@sig21.net>
Signed-off-by: Deepak SIKRI <deepak.sikri@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/stmmac/dwmac1000_core.c')
| -rw-r--r-- | drivers/net/stmmac/dwmac1000_core.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/stmmac/dwmac1000_core.c b/drivers/net/stmmac/dwmac1000_core.c index f1f426146f40..c18c85993179 100644 --- a/drivers/net/stmmac/dwmac1000_core.c +++ b/drivers/net/stmmac/dwmac1000_core.c @@ -50,6 +50,18 @@ static void dwmac1000_core_init(void __iomem *ioaddr) #endif } +static int dwmac1000_rx_coe_supported(void __iomem *ioaddr) +{ + u32 value = readl(ioaddr + GMAC_CONTROL); + + value |= GMAC_CONTROL_IPC; + writel(value, ioaddr + GMAC_CONTROL); + + value = readl(ioaddr + GMAC_CONTROL); + + return !!(value & GMAC_CONTROL_IPC); +} + static void dwmac1000_dump_regs(void __iomem *ioaddr) { int i; @@ -202,6 +214,7 @@ static void dwmac1000_irq_status(void __iomem *ioaddr) struct stmmac_ops dwmac1000_ops = { .core_init = dwmac1000_core_init, + .rx_coe = dwmac1000_rx_coe_supported, .dump_regs = dwmac1000_dump_regs, .host_irq_status = dwmac1000_irq_status, .set_filter = dwmac1000_set_filter, |