diff options
| author |   Matt Carlson <mcarlson@broadcom.com> | 2009-11-13 13:03:40 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2009-11-15 22:14:43 -0800 |
| commit | cbf9ca6cf8304beb640a948709c4672bc1d5a55f (patch) | |
| tree | f1941d408d9db7eb4524fc6423de19f3ef16c342 /drivers/net/tg3.c | |
| parent | tg3: Use tg3_start_xmit_dma_bug for 5717 A0 (diff) | |
| download | linux-dev-cbf9ca6cf8304beb640a948709c4672bc1d5a55f.tar.xz linux-dev-cbf9ca6cf8304beb640a948709c4672bc1d5a55f.zip | |
tg3: Allow DMAs to cross cacheline boundaries
By default, the 5717 (and future chips) break up PCIe DMA packets across
cacheline boundaries. This isn't necessary on x86. This patch
selectively loosens the restriction.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 2d58406deb00..1c1cf68baa94 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7294,9 +7294,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) if (err) return err; - if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 && - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { + val = tr32(TG3PCI_DMA_RW_CTRL) & + ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; + tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); + } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { /* This value is determined during the probe time DMA * engine test, tg3_test_dma. */ @@ -13329,6 +13332,11 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) #endif #endif + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { + val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; + goto out; + } + if (!goal) goto out; @@ -13523,7 +13531,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp) { dma_addr_t buf_dma; u32 *buf, saved_dma_rwctrl; - int ret; + int ret = 0; buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); if (!buf) { @@ -13536,6 +13544,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp) tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) + goto out; + if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { /* DMA read watermark not used on PCIE */ tp->dma_rwctrl |= 0x00180000; @@ -13608,7 +13619,6 @@ static int __devinit tg3_test_dma(struct tg3 *tp) tg3_switch_clocks(tp); #endif - ret = 0; if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) goto out; |