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author | Jeff Johnson <quic_jjohnson@quicinc.com> | 2022-09-09 07:55:35 -0700 |
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committer | Kalle Valo <quic_kvalo@quicinc.com> | 2022-09-16 12:19:14 +0300 |
commit | 3fecca0e7de885c71cf28065015832b78023aa6f (patch) | |
tree | 868d40a7d1214d750d477533c1f5b2839ef5204c /drivers/net/wireless/ath/ath11k/hal.h | |
parent | wifi: ath10k: Fix miscellaneous spelling errors (diff) | |
download | linux-dev-3fecca0e7de885c71cf28065015832b78023aa6f.tar.xz linux-dev-3fecca0e7de885c71cf28065015832b78023aa6f.zip |
wifi: ath11k: Fix miscellaneous spelling errors
Fix misspellings flagged by 'codespell'.
Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20220909145535.20437-1-quic_jjohnson@quicinc.com
Diffstat (limited to 'drivers/net/wireless/ath/ath11k/hal.h')
-rw-r--r-- | drivers/net/wireless/ath/ath11k/hal.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h index e0358062ca2b..01817b4ee5a2 100644 --- a/drivers/net/wireless/ath/ath11k/hal.h +++ b/drivers/net/wireless/ath/ath11k/hal.h @@ -243,7 +243,7 @@ struct ath11k_base; #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 -/* TCL ring feild mask and offset */ +/* TCL ring field mask and offset */ #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) @@ -268,7 +268,7 @@ struct ath11k_base; #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) -/* REO ring feild mask and offset */ +/* REO ring field mask and offset */ #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) @@ -636,7 +636,7 @@ struct hal_srng { } u; }; -/* Interrupt mitigation - Batch threshold in terms of numer of frames */ +/* Interrupt mitigation - Batch threshold in terms of number of frames */ #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 |