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| author |   Carl Huang <cjhuang@codeaurora.org> | 2020-10-01 12:34:44 +0300 |
|---|---|---|
| committer |   Kalle Valo <kvalo@codeaurora.org> | 2020-10-01 22:33:04 +0300 |
| commit | e838c14a9ee1dfe660527128d8f2e3191c8b1aad (patch) | |
| tree | f1443799c80c646bec40919f3ea0eb1c8bb79a13 /drivers/net/wireless/ath/ath11k/hal.h | |
| parent | ath11k: read and write registers below unwindowed address (diff) | |
| download | linux-dev-e838c14a9ee1dfe660527128d8f2e3191c8b1aad.tar.xz linux-dev-e838c14a9ee1dfe660527128d8f2e3191c8b1aad.zip | |
ath11k: enable shadow register configuration and access
To enable shadow register access, host needs to pass shadow
register configuration to firmware via qmi message. Host also
needs to update ring's HP or TP address to shadow register
address. The write operation to shadow register will be
forwarded to target register by hardware automatically, and
the write operation to shadow register is permitted even
when the target is in power save or sleep mode.
Update the shadow config whenever power up happens.
This feature is controlled by hw parameter supports_shadow_regs which is only
enabled for QCA6390.
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1
Signed-off-by: Carl Huang <cjhuang@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1601544890-13450-3-git-send-email-kvalo@codeaurora.org
Diffstat (limited to 'drivers/net/wireless/ath/ath11k/hal.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath11k/hal.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h index 85192d170b6b..fe2448b52a7d 100644 --- a/drivers/net/wireless/ath/ath11k/hal.h +++ b/drivers/net/wireless/ath/ath11k/hal.h @@ -31,8 +31,12 @@ struct ath11k_base; #define HAL_DSCP_TID_TBL_SIZE 24 /* calculate the register address from bar0 of shadow register x */ -#define SHADOW_BASE_ADDRESS 0x00003024 -#define SHADOW_NUM_REGISTERS 36 +#define HAL_SHADOW_BASE_ADDR 0x000008fc +#define HAL_SHADOW_NUM_REGS 36 +#define HAL_HP_OFFSET_IN_REG_START 1 +#define HAL_OFFSET_FROM_HP_TO_TP 4 + +#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) /* WCSS Relative address */ #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 @@ -882,7 +886,7 @@ struct ath11k_hal { u8 current_blk_index; /* shadow register configuration */ - u32 shadow_reg_addr[SHADOW_NUM_REGISTERS]; + u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; int num_shadow_reg_configured; }; @@ -935,5 +939,10 @@ int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, int ath11k_hal_srng_init(struct ath11k_base *ath11k); void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); - +void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, + u32 **cfg, u32 *len); +int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, + enum hal_ring_type ring_type, + int ring_num); +void ath11k_hal_srng_shadow_config(struct ath11k_base *ab); #endif |