diff options
| author |   Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-12-06 16:28:39 +0530 |
|---|---|---|
| committer |   John W. Linville <linville@tuxdriver.com> | 2013-12-09 15:37:56 -0500 |
| commit | 98b2e1fdf1603f30db195a11cc1ffcc2170d42a8 (patch) | |
| tree | 83a80ea1cb9225fb4498ff53047fc56b54cb2588 /drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h | |
| parent | rtlwifi: rtl8192c-common: Fix sparse warning (diff) | |
| download | linux-dev-98b2e1fdf1603f30db195a11cc1ffcc2170d42a8.tar.xz linux-dev-98b2e1fdf1603f30db195a11cc1ffcc2170d42a8.zip | |
ath9k: Add initval arrays for DFS channels
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h index 75bef1179d0d..e6aec2c0207f 100644 --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h @@ -57,8 +57,6 @@ static const u32 ar9580_1p0_baseband_core[][2] = { {0x00009804, 0xfd14e000}, {0x00009808, 0x9c0a9f6b}, {0x0000980c, 0x04900000}, - {0x00009814, 0x3280c00a}, - {0x00009818, 0x00000000}, {0x0000981c, 0x00020028}, {0x00009834, 0x6400a190}, {0x00009838, 0x0108ecff}, @@ -1133,6 +1131,8 @@ static const u32 ar9580_1p0_rx_gain_table[][2] = { static const u32 ar9580_1p0_baseband_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, + {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a}, + {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, @@ -1207,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll_on_clkreq[][2] = { {0x00004044, 0x00000000}, }; +static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = { + /* Addr 5G 2G */ + {0x00009814, 0x3400c00f, 0x3400c00f}, + {0x00009824, 0x5ac668d0, 0x5ac668d0}, + {0x00009828, 0x06903080, 0x06903080}, + {0x00009e0c, 0x6d4000e2, 0x6d4000e2}, + {0x00009e14, 0x37b9625e, 0x37b9625e}, +}; + #endif /* INITVALS_9580_1P0_H */ |