diff options
| author |   Felix Fietkau <nbd@openwrt.org> | 2011-07-09 11:12:51 +0700 |
|---|---|---|
| committer |   John W. Linville <linville@tuxdriver.com> | 2011-07-11 15:02:14 -0400 |
| commit | fe2b6afbce05abe90d31651d3b92c88e0abc5ecb (patch) | |
| tree | 3dc948acb2a9173d31d58e3a21f1ab5b02fbafbf /drivers/net/wireless/ath/ath9k/reg.h | |
| parent | ath9k_hw: initialize more timing related registers for half/quarter channels (diff) | |
| download | linux-dev-fe2b6afbce05abe90d31651d3b92c88e0abc5ecb.tar.xz linux-dev-fe2b6afbce05abe90d31651d3b92c88e0abc5ecb.zip | |
ath9k_hw: remove ar9287 v1.3+ specific hardcoded register hacks
Now that the clock rate is initialized properly and SIFS, EIFS, USEC,
slot time and ACK timeout are properly calculated by the generic code,
the 'async FIFO' register hacks are no longer necessary.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index a4833880accd..759b72cca3cc 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h @@ -600,7 +600,6 @@ #define AR_D_GBL_IFS_SIFS 0x1030 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF -#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF #define AR_D_TXBLK_BASE 0x1038 @@ -616,12 +615,10 @@ #define AR_D_GBL_IFS_SLOT 0x1070 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 -#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 #define AR_D_GBL_IFS_EIFS 0x10b0 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 -#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB #define AR_D_GBL_IFS_MISC 0x10f0 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 @@ -1477,7 +1474,6 @@ enum { #define AR_TIME_OUT_ACK_S 0 #define AR_TIME_OUT_CTS 0x3FFF0000 #define AR_TIME_OUT_CTS_S 16 -#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 #define AR_RSSI_THR 0x8018 #define AR_RSSI_THR_MASK 0x000000FF @@ -1493,7 +1489,6 @@ enum { #define AR_USEC_TX_LAT_S 14 #define AR_USEC_RX_LAT 0x1F800000 #define AR_USEC_RX_LAT_S 23 -#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 #define AR_RESET_TSF 0x8020 #define AR_RESET_TSF_ONCE 0x01000000 |