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| author |   Chi-Hsien Lin <Chi-Hsien.Lin@cypress.com> | 2018-11-21 07:53:50 +0000 |
|---|---|---|
| committer |   Kalle Valo <kvalo@codeaurora.org> | 2018-12-13 16:57:26 +0200 |
| commit | 2f2d389efda4caa4c1b69cb4fa2ab217f0fe6d6f (patch) | |
| tree | 568173ebc824961687e96af74ab9c7822b31fcfb /drivers/net/wireless/broadcom/brcm80211/include | |
| parent | brcmfmac: update 43012 F2 watermark setting to fix DMA Error during UDP RX Traffic (diff) | |
| download | linux-dev-2f2d389efda4caa4c1b69cb4fa2ab217f0fe6d6f.tar.xz linux-dev-2f2d389efda4caa4c1b69cb4fa2ab217f0fe6d6f.zip | |
brcmfmac: 4373 save-restore support
Use chipcommon sr_control0 register to check 4373 sr support.
Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/broadcom/brcm80211/include')
| -rw-r--r-- | drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h index e1fd499930a0..de8225e6248b 100644 --- a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h +++ b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h @@ -269,6 +269,25 @@ struct chipcregs { /* GSIO (spi/i2c) present, rev >= 37 */ #define CC_CAP2_GSIO 0x00000002 +/* sr_control0, rev >= 48 */ +#define CC_SR_CTL0_ENABLE_MASK BIT(0) +#define CC_SR_CTL0_ENABLE_SHIFT 0 +#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ +#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to + * sr_engine + */ +#define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk + * in sr_engine + */ +#define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 +#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 +#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 +#define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power + * domains + */ +#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 +#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 + /* pmucapabilities */ #define PCAP_REV_MASK 0x000000ff #define PCAP_RC_MASK 0x00001f00 |