diff options
| author |   Haim Dreyfuss <haim.dreyfuss@intel.com> | 2016-04-03 19:55:59 +0300 |
|---|---|---|
| committer |   Luca Coelho <luciano.coelho@intel.com> | 2016-05-10 22:14:49 +0300 |
| commit | 1afb0ae4217423f7864cba0684362de99782fa4e (patch) | |
| tree | 3ed4792c760e054596f4301d94c09e6e94be0a63 /drivers/net/wireless/intel/iwlwifi/iwl-csr.h | |
| parent | iwlwifi: wake from runtime suspend before sending sync commands (diff) | |
| download | linux-dev-1afb0ae4217423f7864cba0684362de99782fa4e.tar.xz linux-dev-1afb0ae4217423f7864cba0684362de99782fa4e.zip | |
iwlwifi: allow combining different phy images with mac images
Currently there is one to one function between device id to it's ucode.
The new generation devices allows to combine different phy and mac images.
Now we have two different ucode images with the same device id.
Read RF ID to identify phy image and overwrite it if needed.
Signed-off-by: Haim Dreyfuss <haim.dreyfuss@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'drivers/net/wireless/intel/iwlwifi/iwl-csr.h')
| -rw-r--r-- | drivers/net/wireless/intel/iwlwifi/iwl-csr.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h index b978f6cae55c..b52913448c4a 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h @@ -108,6 +108,17 @@ #define CSR_HW_REV (CSR_BASE+0x028) /* + * RF ID revision info + * Bit fields: + * 31:24: Reserved (set to 0x0) + * 23:12: Type + * 11:8: Step (A - 0x0, B - 0x1, etc) + * 7:4: Dash + * 3:0: Flavor + */ +#define CSR_HW_RF_ID (CSR_BASE+0x09c) + +/* * EEPROM and OTP (one-time-programmable) memory reads * * NOTE: Device must be awake, initialized via apm_ops.init(), @@ -333,6 +344,10 @@ enum { #define CSR_HW_REV_TYPE_7265D (0x0000210) #define CSR_HW_REV_TYPE_NONE (0x00001F0) +/* RF_ID value */ +#define CSR_HW_RF_ID_TYPE_JF (0x00105000) +#define CSR_HW_RF_ID_TYPE_LC (0x00101000) + /* EEPROM REG */ #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) #define CSR_EEPROM_REG_BIT_CMD (0x00000002) |