diff options
| author |   Luca Coelho <luciano.coelho@intel.com> | 2019-12-10 15:11:36 +0200 |
|---|---|---|
| committer | Luca Coelho <luciano.coelho@intel.com> | 2019-12-24 01:34:52 +0200 |
| commit | 3d1b28fd30ab8b87c0935584aff6f9b433939d2c (patch) | |
| tree | e981db3ff1fb041661b8e30239e9dc4d0d9503b6 /drivers/net/wireless/intel | |
| parent | iwlwifi: mvm: fix potential SKB leak on TXQ TX (diff) | |
| download | linux-dev-3d1b28fd30ab8b87c0935584aff6f9b433939d2c.tar.xz linux-dev-3d1b28fd30ab8b87c0935584aff6f9b433939d2c.zip | |
iwlwifi: pcie: rename L0S_ENABLED bit to L0S_DISABLED
This bit has been misnamed since the initial implementation of the
driver. The correct semantics is that setting this bit disables L0S
states, and we already clearly use it as such in the code. Rename it
to avoid confusion.
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'drivers/net/wireless/intel')
| -rw-r--r-- | drivers/net/wireless/intel/iwlwifi/iwl-csr.h | 2 | ||||
| -rw-r--r-- | drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h index 92d9898ab7c2..c2f7252ae4e7 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h @@ -379,7 +379,7 @@ enum { /* CSR GIO */ -#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) +#define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) /* * UCODE-DRIVER GP (general purpose) mailbox register 1 diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index 91fa439d1255..2e599ba2f2ad 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -311,9 +311,9 @@ void iwl_pcie_apm_config(struct iwl_trans *trans) */ pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); if (lctl & PCI_EXP_LNKCTL_ASPM_L1) - iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); + iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); else - iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); + iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); |