diff options
| author |   Eran Harary <eran.harary@intel.com> | 2013-10-02 13:53:40 +0300 |
|---|---|---|
| committer |   Johannes Berg <johannes.berg@intel.com> | 2013-10-11 15:05:02 +0200 |
| commit | e2d6f4e71dc76c815434234cb58c410871888e53 (patch) | |
| tree | 080bf001f3f95bb830cfdca70fffb01c643cb69c /drivers/net/wireless/iwlwifi/iwl-csr.h | |
| parent | iwlwifi: mvm: add IBSS support (diff) | |
| download | linux-dev-e2d6f4e71dc76c815434234cb58c410871888e53.tar.xz linux-dev-e2d6f4e71dc76c815434234cb58c410871888e53.zip | |
iwlwifi: support Signed firmware image and Dual CPUs
Support Signed firmware based on code signing system (CSS)
protocol and dual CPUs download,
the code recognize if there are more than one CPU and
if we need to operate the signed protocol according to
the ucode binary image
Signed-off-by: Eran Harary <eran.harary@intel.com>
Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index a276af476e2d..54a4fdc631b7 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h @@ -394,6 +394,38 @@ #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) +/* SECURE boot registers */ +#define CSR_SECURE_BOOT_CONFIG_ADDR (0x100) +enum secure_boot_config_reg { + CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, + CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, +}; + +#define CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) +#define CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) +enum secure_boot_status_reg { + CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, + CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, + CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, + CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, + CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, +}; + +#define CSR_UCODE_LOAD_STATUS_ADDR (0x100) +enum secure_load_status_reg { + CSR_CPU_STATUS_LOADING_STARTED = 0x00000001, + CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002, + CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, + CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, +}; + +#define CSR_SECURE_INSPECTOR_CODE_ADDR (0x100) +#define CSR_SECURE_INSPECTOR_DATA_ADDR (0x100) + +#define CSR_SECURE_TIME_OUT (100) + +#define FH_TCSR_0_REG0 (0x1D00) + /* * HBUS (Host-side Bus) * |