diff options
| author |   Eran Harary <eran.harary@intel.com> | 2014-01-23 16:26:32 +0200 |
|---|---|---|
| committer |   Emmanuel Grumbach <emmanuel.grumbach@intel.com> | 2014-02-03 22:23:32 +0200 |
| commit | 189fa2faac49bce07c6c6d83eca21cbe5bf47411 (patch) | |
| tree | 359d94bf34ed99a36e201bc5f35190ec5ee9e1f5 /drivers/net/wireless/iwlwifi/iwl-prph.h | |
| parent | iwlwifi: pcie: Disable L0S exit timer for 8000 HW family (diff) | |
| download | linux-dev-189fa2faac49bce07c6c6d83eca21cbe5bf47411.tar.xz linux-dev-189fa2faac49bce07c6c6d83eca21cbe5bf47411.zip | |
iwlwifi: pcie: fix secure section / dual cpu firmware loading
Also handle the bypass mode in which the second CPU doesn't
interfere.
Signed-off-by: Eran Harary <eran.harary@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-prph.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-prph.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index fc3b6bee7734..9c90186d1744 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h @@ -288,4 +288,43 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl) #define OSC_CLK (0xa04068) #define OSC_CLK_FORCE_CONTROL (0x8) +/* SECURE boot registers */ +#define LMPM_SECURE_BOOT_CONFIG_ADDR (0x100) +enum secure_boot_config_reg { + LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, + LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, +}; + +#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR (0x1E30) +#define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR (0x1E34) +enum secure_boot_status_reg { + LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000001, + LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, + LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, + LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, + LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, + LMPM_SECURE_BOOT_STATUS_SUCCESS = 0x00000003, +}; + +#define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70) +enum secure_load_status_reg { + LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, + LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, + LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, + LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, + LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, +}; + +#define LMPM_SECURE_INSPECTOR_CODE_ADDR (0x1E38) +#define LMPM_SECURE_INSPECTOR_DATA_ADDR (0x1E3C) +#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) +#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) + +#define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE (0x400000) +#define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE (0x402000) +#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) +#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) + +#define LMPM_SECURE_TIME_OUT (100) + #endif /* __iwl_prph_h__ */ |