diff options
| author |   Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> | 2014-06-23 23:48:17 +0200 |
|---|---|---|
| committer |   John W. Linville <linville@tuxdriver.com> | 2014-06-25 15:40:32 -0400 |
| commit | 8a607208f522e6b37a93c9258d28d75c15263961 (patch) | |
| tree | 8d398c596adac62c51bddf2ab710d3b8fd443fed /drivers/net/wireless/rtlwifi | |
| parent | b43: N-PHY: update low-pass filter setup (diff) | |
| download | linux-dev-8a607208f522e6b37a93c9258d28d75c15263961.tar.xz linux-dev-8a607208f522e6b37a93c9258d28d75c15263961.zip | |
rtlwifi/rtl8192de: Fix media status register mask
bt_msr & 0xfc will never match 0x3. Fix this by using a mask that actually matches the available types.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Reviewed-by: Peter Wu <peter@lekensteyn.nl>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi')
| -rw-r--r-- | drivers/net/wireless/rtlwifi/rtl8192de/hw.c | 2 | ||||
| -rw-r--r-- | drivers/net/wireless/rtlwifi/rtl8192de/reg.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c index 2b08671004a0..280c3da42993 100644 --- a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c +++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c @@ -1128,7 +1128,7 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw, } rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr); rtlpriv->cfg->ops->led_control(hw, ledaction); - if ((bt_msr & 0xfc) == MSR_AP) + if ((bt_msr & MSR_MASK) == MSR_AP) rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); else rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h index 7f29b8d765b3..315a298bab06 100644 --- a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h +++ b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h @@ -369,6 +369,7 @@ #define MSR_ADHOC 0x01 #define MSR_INFRA 0x02 #define MSR_AP 0x03 +#define MSR_MASK 0x03 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ /* ----------------------------------------------------- */ |