diff options
| author |   Yuval Mintz <Yuval.Mintz@qlogic.com> | 2015-04-29 08:09:49 +0300 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2015-04-29 15:49:21 -0400 |
| commit | 12a8541d5c82d17d42424d46ec36929cfef06a10 (patch) | |
| tree | b3c990dd9bdda48c0f1eecd97db51ccd7f388f2f /drivers/net | |
| parent | net: Fix Kernel Panic in bonding driver debugfs file: rlb_hash_table (diff) | |
| download | linux-dev-12a8541d5c82d17d42424d46ec36929cfef06a10.tar.xz linux-dev-12a8541d5c82d17d42424d46ec36929cfef06a10.zip | |
bnx2x: Delay during kdump load
In a kdump environment interfaces might be re-loaded without a proper
unload sequence in the previous running kernel.
bnx2x management FW and driver maintains a `pulse' that notifies the FW
that the driver is still up and running.
Driver load on the kdump kernel should be performed only after the pulse
has been out-of-sync long enough for the management FW to identify that
the driver has crashed, on which point it will perform some necessary
cleanup of the HW.
In today's distros kdump loading is quite fast, sometimes too fast for our
FW to get out-of-sync. This patch delays the bnx2x's probe during kdump
to allow a proper re-load on the kdump kernel.
Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index 60d2b8ebba16..556dcc162a62 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -13368,6 +13368,12 @@ static int bnx2x_init_one(struct pci_dev *pdev, bool is_vf; int cnic_cnt; + /* Management FW 'remembers' living interfaces. Allow it some time + * to forget previously living interfaces, allowing a proper re-load. + */ + if (is_kdump_kernel()) + msleep(5000); + /* An estimated maximum supported CoS number according to the chip * version. * We will try to roughly estimate the maximum number of CoSes this chip |