diff options
| author |   Lendacky, Thomas <Thomas.Lendacky@amd.com> | 2014-07-29 08:57:43 -0500 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2014-07-30 18:46:53 -0700 |
| commit | 5c10e5cb0fbdde6cc79ca406b8bdcb05aa0c9489 (patch) | |
| tree | 7713fd9ad8d50a62b1865287b1d5179ef56b5034 /drivers/net | |
| parent | amd-xgbe-phy: Updates to rate change complete check (diff) | |
| download | linux-dev-5c10e5cb0fbdde6cc79ca406b8bdcb05aa0c9489.tar.xz linux-dev-5c10e5cb0fbdde6cc79ca406b8bdcb05aa0c9489.zip | |
amd-xgbe-phy: Updates to KR training initiation
As part of changing rates to KR mode, KR training is initiated. If
the KR training is restarted it is possible to enter an invalid logic
state. This can be avoided by asserting a training reset bit before
initiating the KR training and then clearing the training reset bit.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/phy/amd-xgbe-phy.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c index a2d778aefadf..39428e5a1700 100644 --- a/drivers/net/phy/amd-xgbe-phy.c +++ b/drivers/net/phy/amd-xgbe-phy.c @@ -119,10 +119,13 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); #endif /* SerDes integration register offsets */ +#define SIR0_KR_RT_1 0x002c #define SIR0_STATUS 0x0040 #define SIR1_SPEED 0x0000 /* SerDes integration register entry bit positions and sizes */ +#define SIR0_KR_RT_1_RESET_INDEX 11 +#define SIR0_KR_RT_1_RESET_WIDTH 1 #define SIR0_STATUS_RX_READY_INDEX 0 #define SIR0_STATUS_RX_READY_WIDTH 1 #define SIR0_STATUS_TX_READY_INDEX 8 @@ -636,9 +639,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev, if (ret < 0) return AMD_XGBE_AN_ERROR; + XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1); + ret |= 0x01; phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); + XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0); + return AMD_XGBE_AN_EVENT; } |