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authorPrakash Brahmajyosyula <bprakash@marvell.com>2020-03-02 15:29:02 +0530
committerDavid S. Miller <davem@davemloft.net>2020-03-02 11:13:58 -0800
commitaa3afccc9adfff27dbb8f1b92912adbdffa86561 (patch)
tree813d910f021053a6b858eb267554508401d275d8 /drivers/net
parentnet: thunderx: Reduce mbox wait response time. (diff)
downloadlinux-dev-aa3afccc9adfff27dbb8f1b92912adbdffa86561.tar.xz
linux-dev-aa3afccc9adfff27dbb8f1b92912adbdffa86561.zip
net: cavium: Register driver with PCI subsys IDs
Across Cavium's ThunderX and Marvell's OcteonTx2 silicons the PTP timestamping block's PCI device ID and vendor ID have remained same but the HW architecture has changed. Hence added PCI subsystem IDs to the device table to avoid this driver from being probed on OcteonTx2 silicons. Signed-off-by: Prakash Brahmajyosyula <bprakash@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/cavium/common/cavium_ptp.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/ethernet/cavium/common/cavium_ptp.c b/drivers/net/ethernet/cavium/common/cavium_ptp.c
index b821c9e1604c..81ff9ac73f9a 100644
--- a/drivers/net/ethernet/cavium/common/cavium_ptp.c
+++ b/drivers/net/ethernet/cavium/common/cavium_ptp.c
@@ -13,6 +13,9 @@
#define DRV_NAME "cavium_ptp"
#define PCI_DEVICE_ID_CAVIUM_PTP 0xA00C
+#define PCI_SUBSYS_DEVID_88XX_PTP 0xA10C
+#define PCI_SUBSYS_DEVID_81XX_PTP 0XA20C
+#define PCI_SUBSYS_DEVID_83XX_PTP 0xA30C
#define PCI_DEVICE_ID_CAVIUM_RST 0xA00E
#define PCI_PTP_BAR_NO 0
@@ -321,7 +324,12 @@ static void cavium_ptp_remove(struct pci_dev *pdev)
}
static const struct pci_device_id cavium_ptp_id_table[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP) },
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_88XX_PTP) },
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_81XX_PTP) },
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_83XX_PTP) },
{ 0, }
};