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| author |   Rob Herring <robh@kernel.org> | 2020-11-05 15:11:48 -0600 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-11-19 10:51:41 +0000 |
| commit | 458ad06c4cddac4b85f70ee00c295e2c5127ff3c (patch) | |
| tree | b2f3a5e03599485101d655ce0549ab265fd2b236 /drivers/pci/controller/dwc/pcie-designware-host.c | |
| parent | PCI: dwc/intel-gw: Remove some unneeded function wrappers (diff) | |
| download | linux-dev-458ad06c4cddac4b85f70ee00c295e2c5127ff3c.tar.xz linux-dev-458ad06c4cddac4b85f70ee00c295e2c5127ff3c.zip | |
PCI: dwc: Ensure all outbound ATU windows are reset
The Layerscape driver clears the ATU registers which may have been
configured by the bootloader. Any driver could have the same issue
and doing it for all drivers doesn't hurt, so let's move it into the
common DWC code.
Link: https://lore.kernel.org/r/20201105211159.1814485-6-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Minghuan Lian <minghuan.Lian@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: linuxppc-dev@lists.ozlabs.org
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-host.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-host.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index cde45b2076ee..265a48f1a0ae 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -534,6 +534,7 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { + int i; u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -583,6 +584,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + /* Ensure all outbound windows are disabled so there are multiple matches */ + for (i = 0; i < pci->num_viewport; i++) + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); + /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than |