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| author |   Marc Zyngier <maz@kernel.org> | 2021-08-02 17:26:19 +0100 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2021-08-02 11:53:05 -0500 |
| commit | d21faba11693c10072ce3b96b696445175f49be2 (patch) | |
| tree | f7a1957afc5a3db45f0e1456afffcbdd86e44b5c /drivers/pci/controller/pcie-xilinx.c | |
| parent | Linux 5.14-rc1 (diff) | |
| download | linux-dev-d21faba11693c10072ce3b96b696445175f49be2.tar.xz linux-dev-d21faba11693c10072ce3b96b696445175f49be2.zip | |
PCI: Bulk conversion to generic_handle_domain_irq()
Wherever possible, replace constructs that match either
generic_handle_irq(irq_find_mapping()) or
generic_handle_irq(irq_linear_revmap()) to a single call to
generic_handle_domain_irq().
Link: https://lore.kernel.org/r/20210802162630.2219813-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'drivers/pci/controller/pcie-xilinx.c')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 14001febf59a..aa9bdcebc838 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -385,7 +385,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) } if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { - unsigned int irq; + struct irq_domain *domain; val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); @@ -399,19 +399,18 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & XILINX_PCIE_RPIFR2_MSG_DATA; - irq = irq_find_mapping(port->msi_domain->parent, val); + domain = port->msi_domain->parent; } else { val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT; - irq = irq_find_mapping(port->leg_domain, val); + domain = port->leg_domain; } /* Clear interrupt FIFO register 1 */ pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, XILINX_PCIE_REG_RPIFR1); - if (irq) - generic_handle_irq(irq); + generic_handle_domain_irq(domain, val); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP) |