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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2017-09-07 13:24:02 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-07 13:24:02 -0500 |
| commit | 9857f12565792ff077c473e626f00b21286a7f5d (patch) | |
| tree | 6e117efb21c08bf820ca21e09b62e0e65ea6327f /drivers/pci/dwc/pcie-designware.h | |
| parent | Merge branch 'pci/host-kirin' into next (diff) | |
| parent | PCI: layerscape: Add support for ls1088a (diff) | |
| download | linux-dev-9857f12565792ff077c473e626f00b21286a7f5d.tar.xz linux-dev-9857f12565792ff077c473e626f00b21286a7f5d.zip | |
Merge branch 'pci/host-layerscape' into next
* pci/host-layerscape:
PCI: layerscape: Add support for ls1088a
PCI: layerscape: Add support for ls2088a
PCI: artpec6: Stop enabling writes to DBI read-only registers
PCI: layerscape: Remove unnecessary class code fixup
PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates
PCI: dwc: Add accessors for write permission of DBI read-only registers
PCI: layerscape: Disable outbound windows configured by bootloader
PCI: layerscape: Refactor ls1021_pcie_host_init()
PCI: layerscape: Move generic init functions earlier in file
PCI: layerscape: Add class code and multifunction fixups for ls1021a
PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket
PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()
Diffstat (limited to 'drivers/pci/dwc/pcie-designware.h')
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index 7366c8167404..0c5f874345f6 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -76,6 +76,9 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN (0x1 << 0) + /* * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); } +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val |= PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val &= ~PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); |