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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2013-12-09 15:11:25 -0700 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-12-09 15:11:25 -0700 |
| commit | 0b8cfb6aa3aabc96177b1e68ef13d2eb5c686606 (patch) | |
| tree | f73f50a95fffacf1db6ef809012a9930ef3f938c /drivers/pci/host | |
| parent | PCI: designware: Remove redundant call to pci_write_config_word() (diff) | |
| download | linux-dev-0b8cfb6aa3aabc96177b1e68ef13d2eb5c686606.tar.xz linux-dev-0b8cfb6aa3aabc96177b1e68ef13d2eb5c686606.zip | |
PCI: designware: Use typical "for" loop idiom
It's conventional to use "for" rather than "while" for simple iteration.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 5274085ecd4b..1c92833a4ed3 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -214,8 +214,7 @@ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, { unsigned int i, res, bit, val; - i = 0; - while (i < nvec) { + for (i = 0; i < nvec; i++) { irq_set_msi_desc_off(irq_base, i, NULL); clear_bit(pos + i, pp->msi_irq_in_use); /* Disable corresponding interrupt on MSI interrupt controller */ @@ -224,7 +223,6 @@ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); val &= ~(1 << bit); dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); - ++i; } } @@ -268,8 +266,7 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) * descs are also successfully allocated. */ - i = 0; - while (i < no_irqs) { + for (i = 0; i < no_irqs; i++) { if (irq_set_msi_desc_off(irq, i, desc) != 0) { clear_irq_range(pp, irq, i, pos0); goto no_valid_irq; @@ -281,7 +278,6 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); val |= 1 << bit; dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); - i++; } *pos = pos0; |