diff options
| author |   Shaokun Zhang <zhangshaokun@hisilicon.com> | 2018-07-19 19:26:40 +0800 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2018-07-24 15:40:43 +0100 |
| commit | 06060ea7fb5b6b9b4c3251e0dcabbcca8ad91674 (patch) | |
| tree | 7fa83608580ccdbd9602095a246d0a5b07c737e3 /drivers/perf | |
| parent | arm64: perf: Add support for chaining event counters (diff) | |
| download | linux-dev-06060ea7fb5b6b9b4c3251e0dcabbcca8ad91674.tar.xz linux-dev-06060ea7fb5b6b9b4c3251e0dcabbcca8ad91674.zip | |
drivers/perf: hisi: update the sccl_id/ccl_id when MT is supported
MT bit in MPIDR_EL1 is now supported in certain HiSilicon platforms, so
the mapping between sccl_id/ccl_id and affinity level needs to be updated
from the generic encoding we originally used.
Cc: John Garry <john.garry@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
[will: fixed comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_pmu.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index 44df61397a38..9efd2413240c 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -350,19 +350,21 @@ void hisi_uncore_pmu_disable(struct pmu *pmu) /* * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1. - * If multi-threading is supported, SCCL_ID is in MPIDR[aff3] and CCL_ID - * is in MPIDR[aff2]; if not, SCCL_ID is in MPIDR[aff2] and CCL_ID is - * in MPIDR[aff1]. If this changes in future, this shall be updated. + * If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2] + * and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID + * is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1]. */ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id) { u64 mpidr = read_cpuid_mpidr(); if (mpidr & MPIDR_MT_BITMASK) { + int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2); + if (sccl_id) - *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3); + *sccl_id = aff2 >> 3; if (ccl_id) - *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); + *ccl_id = aff2 & 0x7; } else { if (sccl_id) *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); |