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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-14 15:25:04 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-14 15:25:04 -0700 |
commit | b4e1bce85fd8f43dc814049e2641cc6beaa8146b (patch) | |
tree | 4e05c86af9e6c500d04dffede08a8c0b7710a1f8 /drivers/pinctrl/intel/pinctrl-cannonlake.c | |
parent | Merge tag 'leds-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds (diff) | |
parent | pinctrl: amd: Add missing pins to the pin group list (diff) | |
download | linux-dev-b4e1bce85fd8f43dc814049e2641cc6beaa8146b.tar.xz linux-dev-b4e1bce85fd8f43dc814049e2641cc6beaa8146b.zip |
Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- NONE whatsoever, we don't even touch the core files this time
around.
New drivers:
- New driver for the Toshiba Visconti SoC.
- New subdriver for the Qualcomm MSM8226 SoC.
- New subdriver for the Actions Semiconductor S500 SoC.
- New subdriver for the Mediatek MT8192 SoC.
- New subdriver for the Microchip SAMA7G5 SoC.
Driver enhancements:
- Intel Cherryview and Baytrail cleanups and refactorings.
- Enhanced support for the Renesas R8A7790, more pins and groups.
- Some optimizations for the MCP23S08 MCP23x17 variant.
- Some cleanups around the Actions Semiconductor subdrivers.
- A bunch of cleanups around the SH-PFC and Emma Mobile drivers.
- The "SH-PFC" (literally SuperH pin function controller, I think)
subdirectory is now renamed to the more neutral "renesas", as these
are not very much centered around SuperH anymore.
- Non-critical fixes for the Aspeed driver.
- Non-critical fixes for the Ingenic (MIPS!) driver.
- Fix a bunch of missing pins on the AMD pinctrl driver"
* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
pinctrl: amd: Add missing pins to the pin group list
dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
pinctrl: mediatek: Free eint data on failure
pinctrl: single: fix debug output when #pinctrl-cells = 2
pinctrl: single: fix pinctrl_spec.args_count bounds check
pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
pinctrl: tigerlake: Fix register offsets for TGL-H variant
pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
pinctrl: nuvoton: npcm7xx: Constify static ops structs
pinctrl: mediatek: mt7622: add antsel pins/groups
pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
pinctrl: at91-pio4: add support for sama7g5 SoC
dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
pinctrl: spear: simplify the return expression of tvc_connect()
pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
pinctrl: sprd: use module_platform_driver to simplify the code
pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
...
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-cannonlake.c')
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-cannonlake.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 515f57a0d180..8078c7739d6a 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,12 +30,12 @@ .gpio_base = (g), \ } -#define CNL_COMMUNITY(b, s, e, o, g) \ +#define CNL_COMMUNITY(b, s, e, ho, g) \ { \ .barno = (b), \ .padown_offset = CNL_PAD_OWN, \ .padcfglock_offset = CNL_PADCFGLOCK, \ - .hostown_offset = (o), \ + .hostown_offset = (ho), \ .is_offset = CNL_GPI_IS, \ .ie_offset = CNL_GPI_IE, \ .pin_base = (s), \ @@ -44,10 +44,10 @@ .ngpps = ARRAY_SIZE(g), \ } -#define CNLLP_COMMUNITY(b, s, e, g) \ +#define CNL_LP_COMMUNITY(b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g) -#define CNLH_COMMUNITY(b, s, e, g) \ +#define CNL_H_COMMUNITY(b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g) /* Cannon Lake-H */ @@ -449,10 +449,10 @@ static const struct intel_function cnlh_functions[] = { }; static const struct intel_community cnlh_communities[] = { - CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps), - CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps), - CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps), - CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps), + CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps), + CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps), + CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps), + CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps), }; static const struct intel_pinctrl_soc_data cnlh_soc_data = { @@ -810,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = { }; static const struct intel_community cnllp_communities[] = { - CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), - CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), - CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), + CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), + CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), + CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), }; static const struct intel_pinctrl_soc_data cnllp_soc_data = { |