Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.12 cycle.

  The extra week before the merge window actually resulted in some of
  the type of fixes that usually arrive after the merge window already
  starting to trickle in from eager developers using -next, I'm
  impressed.

  I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
  with the onset of Samsung patches. It works great.

  Apart from that it is a boring round, just incremental updates and
  fixes all over the place, no serious core changes or anything exciting
  like that. The most pleasing to see is Julia Cartwrights work to audit
  the irqchip-providing drivers for realtime locking compliance. It's
  one of those "I should really get around to looking into that" things
  that have been on my TODO list since forever.

  Summary:

  Core changes:

   - add bi-directional and output-enable pin configurations to the
     generic bindings and generic pin controlling core.

  New drivers or subdrivers:

   - Armada 37xx SoC pin controller and GPIO support.

   - Axis ARTPEC-6 SoC pin controller support.

   - AllWinner A64 R_PIO controller support, and opening up the
     AllWinner sunxi driver for ARM64 use.

   - Rockchip RK3328 support.

   - Renesas R-Car H3 ES2.0 support.

   - STM32F469 support in the STM32 driver.

   - Aspeed G4 and G5 pin controller support.

  Improvements:

   - a whole slew of realtime improvements to drivers implementing
     irqchips: BCM, AMD, SiRF, sunxi, rockchip.

   - switch meson driver to get the GPIO ranges from the device tree.

   - input schmitt trigger support on the Rockchip driver.

   - enable the sunxi (AllWinner) driver to also be used on ARM64
     silicon.

   - name the Qualcomm QDF2xxx GPIO lines.

   - support GMMR GPIO regions on the Intel Cherryview. This fixes a
     serialization problem on these platforms.

   - pad retention support for the Samsung Exynos 5433.

   - handle suspend-to-ram in the AT91-pio4 driver.

   - pin configuration support in the Aspeed driver.

  Cleanups:

   - the final name of Rockchip RK1108 was RV1108 so rename the driver
     and variables to stay consistent"

* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mediatek: Add missing pinctrl bindings for mt7623
  pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
  pinctrl: artpec6: Remove .owner field for driver
  pinctrl: tegra: xusb: Silence sparse warnings
  ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
  pinctrl: make artpec6 explicitly non-modular
  pinctrl: aspeed: g5: Add pinconf support
  pinctrl: aspeed: g4: Add pinconf support
  pinctrl: aspeed: Add core pinconf support
  pinctrl: aspeed: Document pinconf in devicetree bindings
  pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
  pinctrl: stm32: Add STM32F469 MCU support
  Documentation: dt: Remove ngpios from stm32-pinctrl binding
  pinctrl: stm32: replace device_initcall() with arch_initcall()
  pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
  pinctrl: armada-37xx: Add gpio support
  pinctrl: armada-37xx: Add pin controller support for Armada 37xx
  pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
  pinctrl: core: Make pinctrl_init_controller() static
  pinctrl: generic: Add bi-directional and output-enable
  ...

1 files changed, 49 insertions, 0 deletions

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 31a3a98d067c..9b00be15d258 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -236,6 +236,12 @@ static const unsigned int hdmi_hpd_pins[]	= { PIN(GPIOH_0, EE_OFF) };
 static const unsigned int hdmi_sda_pins[]	= { PIN(GPIOH_1, EE_OFF) };
 static const unsigned int hdmi_scl_pins[]	= { PIN(GPIOH_2, EE_OFF) };
 
+static const unsigned int i2s_out_ch23_y_pins[]	= { PIN(GPIOY_8, EE_OFF) };
+static const unsigned int i2s_out_ch45_y_pins[]	= { PIN(GPIOY_9, EE_OFF) };
+static const unsigned int i2s_out_ch67_y_pins[]	= { PIN(GPIOY_10, EE_OFF) };
+
+static const unsigned int spdif_out_y_pins[]	= { PIN(GPIOY_12, EE_OFF) };
+
 static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
 	MESON_PIN(GPIOAO_0, 0),
 	MESON_PIN(GPIOAO_1, 0),
@@ -274,6 +280,16 @@ static const unsigned int pwm_ao_a_6_pins[]	= { PIN(GPIOAO_6, 0) };
 static const unsigned int pwm_ao_a_12_pins[]	= { PIN(GPIOAO_12, 0) };
 static const unsigned int pwm_ao_b_pins[]	= { PIN(GPIOAO_13, 0) };
 
+static const unsigned int i2s_am_clk_pins[]	 = { PIN(GPIOAO_8, 0) };
+static const unsigned int i2s_out_ao_clk_pins[]	 = { PIN(GPIOAO_9, 0) };
+static const unsigned int i2s_out_lr_clk_pins[]	 = { PIN(GPIOAO_10, 0) };
+static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, 0) };
+static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_12, 0) };
+static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_13, 0) };
+
+static const unsigned int spdif_out_ao_6_pins[]	= { PIN(GPIOAO_6, 0) };
+static const unsigned int spdif_out_ao_13_pins[] = { PIN(GPIOAO_13, 0) };
+
 static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GPIO_GROUP(GPIOZ_0, EE_OFF),
 	GPIO_GROUP(GPIOZ_1, EE_OFF),
@@ -426,6 +442,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(uart_rx_c,	1,	16),
 	GROUP(pwm_a_y,		1,	21),
 	GROUP(pwm_f_y,		1,	20),
+	GROUP(i2s_out_ch23_y,	1,	5),
+	GROUP(i2s_out_ch45_y,	1,	6),
+	GROUP(i2s_out_ch67_y,	1,	7),
+	GROUP(spdif_out_y,	1,	9),
 
 	/* Bank Z */
 	GROUP(eth_mdio,		6,	1),
@@ -523,6 +543,14 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
 	GROUP(pwm_ao_a_6,	0,	18),
 	GROUP(pwm_ao_a_12,	0,	17),
 	GROUP(pwm_ao_b,		0,	3),
+	GROUP(i2s_am_clk,	0,	30),
+	GROUP(i2s_out_ao_clk,	0,	29),
+	GROUP(i2s_out_lr_clk,	0,	28),
+	GROUP(i2s_out_ch01_ao,	0,	27),
+	GROUP(i2s_out_ch23_ao,	1,	0),
+	GROUP(i2s_out_ch45_ao,	1,	1),
+	GROUP(spdif_out_ao_6,	0,	16),
+	GROUP(spdif_out_ao_13,	0,	4),
 };
 
 static const char * const gpio_periphs_groups[] = {
@@ -652,6 +680,14 @@ static const char * const hdmi_i2c_groups[] = {
 	"hdmi_sda", "hdmi_scl",
 };
 
+static const char * const i2s_out_groups[] = {
+	"i2s_out_ch23_y", "i2s_out_ch45_y", "i2s_out_ch67_y",
+};
+
+static const char * const spdif_out_groups[] = {
+	"spdif_out_y",
+};
+
 static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
@@ -694,6 +730,15 @@ static const char * const pwm_ao_b_groups[] = {
 	"pwm_ao_b",
 };
 
+static const char * const i2s_out_ao_groups[] = {
+	"i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk",
+	"i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao",
+};
+
+static const char * const spdif_out_ao_groups[] = {
+	"spdif_out_ao_6", "spdif_out_ao_13",
+};
+
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
@@ -717,6 +762,8 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(pwm_f_y),
 	FUNCTION(hdmi_hpd),
 	FUNCTION(hdmi_i2c),
+	FUNCTION(i2s_out),
+	FUNCTION(spdif_out),
 };
 
 static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
@@ -730,6 +777,8 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
 	FUNCTION(pwm_ao_a_6),
 	FUNCTION(pwm_ao_a_12),
 	FUNCTION(pwm_ao_b),
+	FUNCTION(i2s_out_ao),
+	FUNCTION(spdif_out_ao),
 };
 
 static struct meson_bank meson_gxbb_periphs_banks[] = {