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| author |   Chris Packham <chris.packham@alliedtelesis.co.nz> | 2018-05-04 15:06:37 +1200 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2018-05-23 11:09:09 +0200 |
| commit | f61f5a2174cd7534f128dc26e2fe7de56cb08a3c (patch) | |
| tree | 44ddfca688f64a4a59aa70762a96d5212ee16f9d /drivers/pinctrl/mvebu | |
| parent | MAINTAINERS: Add Actions Semi S900 pinctrl entries (diff) | |
| download | linux-dev-f61f5a2174cd7534f128dc26e2fe7de56cb08a3c.tar.xz linux-dev-f61f5a2174cd7534f128dc26e2fe7de56cb08a3c.zip | |
pinctrl: mvebu: update use "nand" function for "rb" pin
The Armada 98dx3236 SoCs don't have a different MPP sel value for nand
specific pins so "dev" was technically correct. But all the other Armada
SoCs use "nand" in their dts and the pin is specific to the nand
interface so use "nand" for the function name.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mvebu')
| -rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index e732f3a1efb7..5e828468e43d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -431,7 +431,7 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { MPP_MODE(19, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "nand", "rb", V_98DX3236_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), |