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| author |   Jason Gunthorpe <jgunthorpe@obsidianresearch.com> | 2016-10-26 12:04:54 -0600 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2016-11-04 15:19:00 +0100 |
| commit | 951f033d969a6deff668286ed4bf0783f905a413 (patch) | |
| tree | d5934425757746a3a222618159c096cdaf61c68e /drivers/pinctrl/pinctrl-zynq.c | |
| parent | pinctrl: at91: add support for OUTPUT config (diff) | |
| download | linux-dev-951f033d969a6deff668286ed4bf0783f905a413.tar.xz linux-dev-951f033d969a6deff668286ed4bf0783f905a413.zip | |
pinctrl: zynq: Add a 8 bit wide nand option
The hardware supports a 16 and 8 bit wide NAND bus, let users pick
either.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-zynq.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-zynq.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index e0ecffcbe11f..b51a46dfdcc3 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -247,6 +247,8 @@ static const unsigned int smc0_nor_addr25_pins[] = {1}; static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23}; +static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14}; /* Note: CAN MIO clock inputs are modeled in the clock framework */ static const unsigned int can0_0_pins[] = {10, 11}; static const unsigned int can0_1_pins[] = {14, 15}; @@ -445,6 +447,7 @@ static const struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1), DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25), DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand), + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8), DEFINE_ZYNQ_PINCTRL_GRP(can0_0), DEFINE_ZYNQ_PINCTRL_GRP(can0_1), DEFINE_ZYNQ_PINCTRL_GRP(can0_2), @@ -709,7 +712,8 @@ static const char * const sdio1_wp_groups[] = {"gpio0_0_grp", static const char * const smc0_nor_groups[] = {"smc0_nor_grp"}; static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; -static const char * const smc0_nand_groups[] = {"smc0_nand_grp"}; +static const char * const smc0_nand_groups[] = {"smc0_nand_grp", + "smc0_nand8_grp"}; static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", |