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| author |   Chanwoo Choi <cw00.choi@samsung.com> | 2016-12-30 13:14:18 +0900 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2016-12-30 14:27:42 +0100 |
| commit | 1259feddd0f83649d5c48d730c140b4f7f3fa288 (patch) | |
| tree | 6924dfc6eff3b7c5f99767e129b2ffb33b5973a4 /drivers/pinctrl/samsung/pinctrl-exynos.h | |
| parent | pinctrl: meson: fix gpio request disabling other modes (diff) | |
| download | linux-dev-1259feddd0f83649d5c48d730c140b4f7f3fa288.tar.xz linux-dev-1259feddd0f83649d5c48d730c140b4f7f3fa288.zip | |
pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.
Fixes: 3c5ecc9ed353 ("pinctrl: exynos: Add support for Exynos5433")
Cc: stable@vger.kernel.org
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/samsung/pinctrl-exynos.h')
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 5821525a2c84..a473092fb8d2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -90,6 +90,37 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos5433_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos5433_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ + { \ + .type = &exynos5433_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id, \ + .pctl_res_idx = pctl_idx, \ + } \ + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. |