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| author |   Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-31 17:05:14 +0900 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2016-05-31 12:46:18 +0200 |
| commit | 72e5706aa786f6640b229717b7d9d537058c59cf (patch) | |
| tree | 8e14a67f1e887411ac0dbdcd5daa139b18eeb3c4 /drivers/pinctrl/uniphier/pinctrl-uniphier.h | |
| parent | pinctrl: uniphier: rename macros for drive strength control (diff) | |
| download | linux-dev-72e5706aa786f6640b229717b7d9d537058c59cf.tar.xz linux-dev-72e5706aa786f6640b229717b7d9d537058c59cf.zip | |
pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier.h')
| -rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 7f3e7ffe0096..eca379a2b976 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -25,6 +25,7 @@ struct platform_device; #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900 +#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00 #define UNIPHIER_PINCTRL_IECTRL 0xd00 @@ -72,6 +73,7 @@ struct platform_device; enum uniphier_pin_drv_type { UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */ UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */ + UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */ UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */ UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */ UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */ |