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authorTomasz Figa <tomasz.figa@gmail.com>2013-03-18 22:31:54 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-04-09 09:43:39 +0200
commitc16150d846585d27e90795447ecc7c055d90f6d5 (patch)
tree7a856e8bcb2440f8d6f641e34e1bd90cd97d147a /drivers/pinctrl
parentpinctrl: samsung: Remove hardcoded register offsets (diff)
downloadlinux-dev-c16150d846585d27e90795447ecc7c055d90f6d5.tar.xz
linux-dev-c16150d846585d27e90795447ecc7c055d90f6d5.zip
pinctrl: samsung: Handle banks with two configuration registers
This patch adds support for banks that have more than one function configuration registers, e.g. some of the banks of S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index b917ed36fb65..8b15c6622b33 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -303,6 +303,11 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
type = bank->type;
mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
+ if (shift >= 32) {
+ /* Some banks have two config registers */
+ shift -= 32;
+ reg += 4;
+ }
spin_lock_irqsave(&bank->slock, flags);
@@ -356,6 +361,11 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
+ if (shift >= 32) {
+ /* Some banks have two config registers */
+ shift -= 32;
+ reg += 4;
+ }
spin_lock_irqsave(&bank->slock, flags);