diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2015-03-12 11:09:13 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2015-03-18 02:12:47 +0100 |
| commit | dc70071550c2b8b1185d086b0f1954dfbc63aee2 (patch) | |
| tree | 3dafc1679ca18cb8f7c544251ccee2054a8097f6 /drivers/pinctrl | |
| parent | pinctrl: add AMD GPIO driver support. (diff) | |
| download | linux-dev-dc70071550c2b8b1185d086b0f1954dfbc63aee2.tar.xz linux-dev-dc70071550c2b8b1185d086b0f1954dfbc63aee2.zip | |
pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned long
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.
This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs by 26460 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/core.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/sh-pfc/sh_pfc.h | 10 |
2 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 895a41e2f30a..5591baf9738b 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -209,7 +209,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); dev_dbg(pfc->dev, "write_reg addr = %lx, value = 0x%x, field = %ld, " - "r_width = %ld, f_width = %ld\n", + "r_width = %u, f_width = %u\n", crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index ed5cf4192fa1..6aeec8152ea6 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -69,9 +69,10 @@ struct pinmux_func { }; struct pinmux_cfg_reg { - unsigned long reg, reg_width, field_width; + unsigned long reg; + u8 reg_width, field_width; const u16 *enum_ids; - const unsigned long *var_field_width; + const u8 *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ @@ -80,12 +81,13 @@ struct pinmux_cfg_reg { #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .var_field_width = (const unsigned long [r_width]) \ + .var_field_width = (const u8 [r_width]) \ { var_fw0, var_fwn, 0 }, \ .enum_ids = (const u16 []) struct pinmux_data_reg { - unsigned long reg, reg_width; + unsigned long reg; + u8 reg_width; const u16 *enum_ids; }; |