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| author |   Box, David E <david.e.box@intel.com> | 2018-06-08 17:02:37 -0700 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2018-07-02 15:00:30 +0300 |
| commit | 4cf2afd6ef0d5e43e92d46401e7c1d3a9fac915b (patch) | |
| tree | 387567a143a538f806ede4d6c3c9702152ad2a11 /drivers/platform/x86/intel_pmc_core.h | |
| parent | platform/x86: Rename silead_dmi to touchscreen_dmi (diff) | |
| download | linux-dev-4cf2afd6ef0d5e43e92d46401e7c1d3a9fac915b.tar.xz linux-dev-4cf2afd6ef0d5e43e92d46401e7c1d3a9fac915b.zip | |
platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers
Adds debugfs access to registers in the Cannon Point PCH PMC that are
useful for debugging #SLP_S0 signal assertion and other low power relate
activities. Device pm states are latched in these registers whenever the
package enters C10 and can be read from slp_s0_debug_status. The pm
states may also be latched by writing 1 to slp_s0_dbg_latch which will
immediately capture the current state on the next read of
slp_s0_debug_status.
Signed-off-by: Box, David E <david.e.box@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 5fa5f97870aa..93a7e99e1f8b 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -127,12 +127,14 @@ enum ppfear_regs { #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C #define CNP_PMC_PM_CFG_OFFSET 0x1818 +#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ #define CNP_PMC_HOST_PPFEAR0A 0x1D90 #define CNP_PMC_MMIO_REG_LEN 0x2000 #define CNP_PPFEAR_NUM_ENTRIES 8 #define CNP_PMC_READ_DISABLE_BIT 22 +#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) struct pmc_bit_map { const char *name; @@ -145,6 +147,7 @@ struct pmc_bit_map { * @pfear_sts: Maps name of IP block to PPFEAR* bit * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit * @pll_sts: Maps name of PLL to corresponding bit status + * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit * @regmap_length: Length of memory to map from PWRMBASE address to access @@ -153,6 +156,7 @@ struct pmc_bit_map { * PPFEAR * @pm_cfg_offset: PWRMBASE offset to PM_CFG register * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE + * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* * * Each PCH has unique set of register offsets and bit indexes. This structure * captures them to have a common implementation. @@ -161,6 +165,7 @@ struct pmc_reg_map { const struct pmc_bit_map *pfear_sts; const struct pmc_bit_map *mphy_sts; const struct pmc_bit_map *pll_sts; + const struct pmc_bit_map **slps0_dbg_maps; const u32 slp_s0_offset; const u32 ltr_ignore_offset; const int regmap_length; @@ -168,6 +173,7 @@ struct pmc_reg_map { const int ppfear_buckets; const u32 pm_cfg_offset; const int pm_read_disable_bit; + const u32 slps0_dbg_offset; }; /** |