diff options
| author |   Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> | 2018-11-09 00:32:44 +0530 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2018-11-10 16:28:10 +0200 |
| commit | 8122e7cd806df4c696eed0c9a6ad1e69dfe783fc (patch) | |
| tree | c1c5f6f3e5f9e988c9e5817bb241d6fbf1ef35d9 /drivers/platform/x86/intel_pmc_core.h | |
| parent | platform/x86: intel_pmc_core: Fix LTR IGNORE Max offset (diff) | |
| download | linux-dev-8122e7cd806df4c696eed0c9a6ad1e69dfe783fc.tar.xz linux-dev-8122e7cd806df4c696eed0c9a6ad1e69dfe783fc.zip | |
platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR
The LTR values follow PCIE LTR encoding format and can be decoded as per
https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf
This adds support to translate the raw LTR values as read from the PMC
to meaningful values in nanosecond units of time.
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index e57b26cdb442..89554cba5758 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -12,6 +12,8 @@ #ifndef PMC_CORE_H #define PMC_CORE_H +#include <linux/bits.h> + #define PMC_BASE_ADDR_DEFAULT 0xFE000000 /* Sunrise Point Power Management Controller PCI Device ID */ @@ -169,6 +171,11 @@ enum ppfear_regs { #define CNP_PMC_LTR_EMMC 0x1BF4 #define CNP_PMC_LTR_UFSX2 0x1BF8 +#define LTR_DECODED_VAL GENMASK(9, 0) +#define LTR_DECODED_SCALE GENMASK(12, 10) +#define LTR_REQ_SNOOP BIT(15) +#define LTR_REQ_NONSNOOP BIT(31) + struct pmc_bit_map { const char *name; u32 bit_mask; |