diff options
| author |   Xiang Chen <chenxiang66@hisilicon.com> | 2019-05-29 17:58:47 +0800 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2019-06-18 19:46:24 -0400 |
| commit | 97fcf176b43bedcfd64cca5fd7e07e2cd2bde284 (patch) | |
| tree | 613cd4433f1a4a130b85fb347e02322a2f561adc /drivers/scsi/hisi_sas | |
| parent | scsi: hisi_sas: Ignore the error code between phy down to phy up (diff) | |
| download | linux-dev-97fcf176b43bedcfd64cca5fd7e07e2cd2bde284.tar.xz linux-dev-97fcf176b43bedcfd64cca5fd7e07e2cd2bde284.zip | |
scsi: hisi_sas: Disable stash for v3 hw
For v3 hw, stash is enabled to promote performance, but it does little to
improve performance according to current tests. What's more, it causes
exceptions for some situations, so disable it.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/hisi_sas')
| -rw-r--r-- | drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index fbf0a1e9c8c2..b92aa6b37e1d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -28,6 +28,7 @@ #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) #define ITCT_DEV_OFF 0 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) +#define SAS_AXI_USER3 0x50 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 @@ -554,6 +555,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) /* Global registers init */ hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, (u32)((1ULL << hisi_hba->queue_count) - 1)); + hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0); hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); |