diff options
| author |   Chaitra P B <chaitra.basappa@broadcom.com> | 2018-04-24 05:28:41 -0400 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2018-05-08 00:39:49 -0400 |
| commit | c1a6c5ac4278d406c112cc2f038e6e506feadff9 (patch) | |
| tree | 4bbd8b6fa1b89ca29b05369db062b131ac309018 /drivers/scsi/mpt3sas/mpt3sas_ctl.c | |
| parent | scsi: mpt3sas: Update MPI Headers (diff) | |
| download | linux-dev-c1a6c5ac4278d406c112cc2f038e6e506feadff9.tar.xz linux-dev-c1a6c5ac4278d406c112cc2f038e6e506feadff9.zip | |
scsi: mpt3sas: For NVME device, issue a protocol level reset
1) Manufacturing Page 11 contains parameters to control internal
firmware behavior. Based on AddlFlags2 field FW/Driver behaviour can
be changed, (flag tm_custom_handling is used for this)
a) For PCIe device, protocol level reset should be used if flag
tm_custom_handling is 0. Since Abort Task Set, LUN reset and Target
reset will result in a protocol level reset. Drivers should issue
only one type of this reset, if that fails then it should escalate to
a controller reset (diag reset/OCR).
b) If the driver has control over the TM reset timeout value, then
driver should use the value exposed in PCIe Device Page 2 for pcie
device (field ControllerResetTO).
Signed-off-by: Chaitra P B <chaitra.basappa@broadcom.com>
Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/mpt3sas/mpt3sas_ctl.c')
| -rw-r--r-- | drivers/scsi/mpt3sas/mpt3sas_ctl.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/drivers/scsi/mpt3sas/mpt3sas_ctl.c b/drivers/scsi/mpt3sas/mpt3sas_ctl.c index c1b17d64c95f..3269ef43f07e 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_ctl.c +++ b/drivers/scsi/mpt3sas/mpt3sas_ctl.c @@ -644,9 +644,10 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg, MPI2RequestHeader_t *mpi_request = NULL, *request; MPI2DefaultReply_t *mpi_reply; Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request = NULL; + struct _pcie_device *pcie_device = NULL; u32 ioc_state; u16 smid; - unsigned long timeout; + u8 timeout; u8 issue_reset; u32 sz, sz_arg; void *psge; @@ -659,6 +660,7 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg, long ret; u16 wait_state_count; u16 device_handle = MPT3SAS_INVALID_DEVICE_HANDLE; + u8 tr_method = MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE; issue_reset = 0; @@ -1074,14 +1076,26 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg, ioc->name, le16_to_cpu(mpi_request->FunctionDependent1)); mpt3sas_halt_firmware(ioc); - mpt3sas_scsih_issue_locked_tm(ioc, - le16_to_cpu(mpi_request->FunctionDependent1), 0, - MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 0, 30); + pcie_device = mpt3sas_get_pdev_by_handle(ioc, + le16_to_cpu(mpi_request->FunctionDependent1)); + if (pcie_device && (!ioc->tm_custom_handling)) + mpt3sas_scsih_issue_locked_tm(ioc, + le16_to_cpu(mpi_request->FunctionDependent1), + 0, MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, + 0, pcie_device->reset_timeout, + tr_method); + else + mpt3sas_scsih_issue_locked_tm(ioc, + le16_to_cpu(mpi_request->FunctionDependent1), + 0, MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, + 0, 30, MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET); } else mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); } out: + if (pcie_device) + pcie_device_put(pcie_device); /* free memory associated with sg buffers */ if (data_in) |