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| author |   Can Guo <cang@codeaurora.org> | 2019-12-05 02:14:42 +0000 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2019-12-19 22:08:53 -0500 |
| commit | 0834253734cbb40c312c06e5beb9b94ac7cf5e80 (patch) | |
| tree | f3b72cf87483f5c8cb9b55e748591fdc5c5ffbe6 /drivers/scsi/ufs/ufshcd.c | |
| parent | scsi: ufs: Release clock if DMA map fails (diff) | |
| download | linux-dev-0834253734cbb40c312c06e5beb9b94ac7cf5e80.tar.xz linux-dev-0834253734cbb40c312c06e5beb9b94ac7cf5e80.zip | |
scsi: ufs: Do not clear the DL layer timers
During power mode change, PACP_PWR_Req frame sends PAPowerModeUserData
parameters (and they are considered valid by device if Flags[4] -
UserDataValid bit is set in the same frame). Currently we don't set these
PAPowerModeUserData parameters and hardware always sets UserDataValid bit
which would clear all the DL layer timeout values of the peer device after
the power mode change.
This change sets the PAPowerModeUserData[0..5] to UniPro specification
recommended default values, in addition we are also setting the relevant
DME_LOCAL_* timer attributes as required by UFS HCI specification.
Link: https://lore.kernel.org/r/0101016ed3d688a4-cfaeb1c9-238b-46c4-9c89-d48c410ba325-000000@us-west-2.amazonses.com
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Signed-off-by: Can Guo <cang@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/ufs/ufshcd.c')
| -rw-r--r-- | drivers/scsi/ufs/ufshcd.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 64abb30d990a..c1f92ee5391a 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -4033,6 +4033,26 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba, ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), pwr_mode->hs_rate); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), + DL_FC0ProtectionTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), + DL_TC0ReplayTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), + DL_AFC0ReqTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), + DL_FC1ProtectionTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), + DL_TC1ReplayTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), + DL_AFC1ReqTimeOutVal_Default); + + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), + DL_FC0ProtectionTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), + DL_TC0ReplayTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), + DL_AFC0ReqTimeOutVal_Default); + ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | pwr_mode->pwr_tx); |