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authorZhao Qiang <qiang.zhao@freescale.com>2015-11-30 10:48:57 +0800
committerScott Wood <scottwood@freescale.com>2015-12-22 17:12:56 -0600
commit7aa1aa6ecec2af19d9aa85430ce3e56119e21626 (patch)
tree0acc8cf320d38abb5bdb12ff8df6053dfa612dd0 /drivers/soc/fsl/qe/Kconfig
parentQE: use subsys_initcall to init qe (diff)
downloadlinux-dev-7aa1aa6ecec2af19d9aa85430ce3e56119e21626.tar.xz
linux-dev-7aa1aa6ecec2af19d9aa85430ce3e56119e21626.zip
QE: Move QE from arch/powerpc to drivers/soc
ls1 has qe and ls1 has arm cpu. move qe from arch/powerpc to drivers/soc/fsl to adapt to powerpc and arm Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers/soc/fsl/qe/Kconfig')
-rw-r--r--drivers/soc/fsl/qe/Kconfig38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
new file mode 100644
index 000000000000..20978f2058a6
--- /dev/null
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -0,0 +1,38 @@
+#
+# QE Communication options
+#
+
+config QUICC_ENGINE
+ bool "Freescale QUICC Engine (QE) Support"
+ depends on FSL_SOC && PPC32
+ select GENERIC_ALLOCATOR
+ select CRC32
+ help
+ The QUICC Engine (QE) is a new generation of communications
+ coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
+ Selecting this option means that you wish to build a kernel
+ for a machine with a QE coprocessor.
+
+config UCC_SLOW
+ bool
+ default y if SERIAL_QE
+ help
+ This option provides qe_lib support to UCC slow
+ protocols: UART, BISYNC, QMC
+
+config UCC_FAST
+ bool
+ default y if UCC_GETH
+ help
+ This option provides qe_lib support to UCC fast
+ protocols: HDLC, Ethernet, ATM, transparent
+
+config UCC
+ bool
+ default y if UCC_FAST || UCC_SLOW
+
+config QE_USB
+ bool
+ default y if USB_FSL_QE
+ help
+ QE USB Controller support